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http://ir.lib.seu.ac.lk/handle/123456789/2199
Title: | An approach for automatic design of application specific instruction set processors (ASIP) |
Authors: | Mansoor, C.M.M. |
Keywords: | Application specific instruction set processor (ASIP) Custom processor Embedded system MIPS |
Issue Date: | 17-Jan-2017 |
Publisher: | Faculty of Arts & Culture, South Eastern University of Sri Lanka |
Citation: | 5th South Eastern University Arts Research Session 2016 on "Research and Development for a Global Knowledge Society". 17 January 2017. South Eastern University of Sri Lanka, Oluvil, Sri Lanka. |
Abstract: | Today‟s hectic world is primarily dominated by electronics. The use of large and hard electronic devices is rapidly being replaced with simple, light and easy-to-carry ones. The past was primarily filled with the notion of performing varied tasks under one roof and the gadgets were built to serve that purpose through the introduction of General Purpose Processors (GPPs) into them. On the contrary, the present tendency is towards devices that are able to perform specific tasks. In the line of this modern concept, the world of embedded system is chiefly dominated by Application Specific Instruction set Processors (ASIPs) because they are geared to perform specific tasks without placing heavy burdens in many respects on the part of the users. Application Specific Instruction set Processors (ASIP), also known as customized processorsare processors designed for particular applications or, for a set of applications.They can be optimized for speed, chip area, and power consumption taking advantage of the flexibility of a synthesized semi-custom implementation. The development of application-specific instruction- set processors is currently the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that building such an architecture is a difficult task that requires expertise in different domains. The main aim of this paper is to propose an approach that will automatically design an ASIP based on the application requirement, which is given as the input to the system. We propose to achieve the same by analyzing different types of RISCMIPS assembly instructions to map the corresponding target VHDL processor to customize maximize the memory access and components of the central processing unit and count the occurrences for the 32-bit RISC CPU based on MIPS. In this work, we also analyze MIPS instruction format, instruction data path, RISC CPU instruction set. |
URI: | http://ir.lib.seu.ac.lk/handle/123456789/2199 |
ISBN: | 978-955-627-100-3 |
Appears in Collections: | SEUARS 2016 |
Files in This Item:
File | Description | Size | Format | |
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ICT - Page 30-34.pdf | Information & Communication Technology | 453.1 kB | Adobe PDF | View/Open |
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